Hi everyone,
I have a series of 8 or 9 subroutines that are not in the main program file (File 2)..they are all consecutively placed in Ladder 11.
As the machine does what its supposed to, in File 11, one subroutine, then the next, then the next become active processes. Currently I have an archaic way of ensuring the subroutines that are not needed do not execute (all rungs in these subs are conditional based on one bit assigned to that subroutine...(ie for example Tank Fill Active) So the processor has to scan thru all subroutines, one after the other, even though only one is going to make the machine do something at any given time.
I did it this way because I was in a hurry, did not have time to research, I was taught that conditional subroutines are a bad idea, so I chose not to put a controlling bit in front of each and every subroutine, i wanted them all to get scanned.
Now, of course, I wish to make this program scan more streamlined. Within each subroutine, I looked at putting a XIO and a RET on the first rung, (the XIO is on the bit that enables/disables the whole subroutine) but apparently according to the help files, this will cause the scan to go back to the previous subroutine. Only if the series of subroutines are actually in the main file (File 2) will a RET cause the scan to jump to the NEXT subroutine, which is what I want. Is this correct?
Also, it seems that if I use JMP and LBL, (JMP on the first rung based on the enable bit, and LBL on the last rung), that looks like it would work but LBL is an input instruction and RS500 wants me to at least put some dummy coil on that LBL rung as an output instruction just to make it happy. Is this a dumb idea even though it would seemingly solve my issue?
Any tips would be appreciated!
I have a series of 8 or 9 subroutines that are not in the main program file (File 2)..they are all consecutively placed in Ladder 11.
As the machine does what its supposed to, in File 11, one subroutine, then the next, then the next become active processes. Currently I have an archaic way of ensuring the subroutines that are not needed do not execute (all rungs in these subs are conditional based on one bit assigned to that subroutine...(ie for example Tank Fill Active) So the processor has to scan thru all subroutines, one after the other, even though only one is going to make the machine do something at any given time.
I did it this way because I was in a hurry, did not have time to research, I was taught that conditional subroutines are a bad idea, so I chose not to put a controlling bit in front of each and every subroutine, i wanted them all to get scanned.
Now, of course, I wish to make this program scan more streamlined. Within each subroutine, I looked at putting a XIO and a RET on the first rung, (the XIO is on the bit that enables/disables the whole subroutine) but apparently according to the help files, this will cause the scan to go back to the previous subroutine. Only if the series of subroutines are actually in the main file (File 2) will a RET cause the scan to jump to the NEXT subroutine, which is what I want. Is this correct?
Also, it seems that if I use JMP and LBL, (JMP on the first rung based on the enable bit, and LBL on the last rung), that looks like it would work but LBL is an input instruction and RS500 wants me to at least put some dummy coil on that LBL rung as an output instruction just to make it happy. Is this a dumb idea even though it would seemingly solve my issue?
Any tips would be appreciated!