Mark Snodgrass
Member
I want to clear up what Seth said, so you understand what synchronous and asynchronous mean.
The PLC5, Slc500 Family processors cycles in a certain order:
1. Scans the input conditions and writes that data to the data table.
2. Scans the program left to right, top down until it comes to end of main routine (it will jump out for subroutines, but will return to the same spot).
3. Reads the data table and turns outputs on or off based on the data table.
4. Performs PLC overhead and housekeeping
5. Return to 1.
The RS5000 Family of processors cycles differently which has an effect of speeding up the overall scan time.
The program scans right to left, top down same as the PLC5s but the inputs are updated by the input module at a scheduled interval. The inputs can change anytime within the execution of the logic. The output modules read the data at a scheduled interval.
What this does is if you use an input early in the logic, it may change before the logic uses it near the end of the logic. This can give unexpected results to the logic. Also outputs may not change when you expect them to. This can be a problem with large slow programs and/or fats processes. What the 'mapping' does is to at the beginning of the program we set internal bits with the status of the inputs, so they stay the same throughout the entire scan. Then at the end of the program the outputs are 'mapped' so that all the logic has been completed before changing what the physical outputs do.
Look at Ron Beaufort's videos that I gave you the link to and it explains it a bit clearer than I can.
The PLC5, Slc500 Family processors cycles in a certain order:
1. Scans the input conditions and writes that data to the data table.
2. Scans the program left to right, top down until it comes to end of main routine (it will jump out for subroutines, but will return to the same spot).
3. Reads the data table and turns outputs on or off based on the data table.
4. Performs PLC overhead and housekeeping
5. Return to 1.
The RS5000 Family of processors cycles differently which has an effect of speeding up the overall scan time.
The program scans right to left, top down same as the PLC5s but the inputs are updated by the input module at a scheduled interval. The inputs can change anytime within the execution of the logic. The output modules read the data at a scheduled interval.
What this does is if you use an input early in the logic, it may change before the logic uses it near the end of the logic. This can give unexpected results to the logic. Also outputs may not change when you expect them to. This can be a problem with large slow programs and/or fats processes. What the 'mapping' does is to at the beginning of the program we set internal bits with the status of the inputs, so they stay the same throughout the entire scan. Then at the end of the program the outputs are 'mapped' so that all the logic has been completed before changing what the physical outputs do.
Look at Ron Beaufort's videos that I gave you the link to and it explains it a bit clearer than I can.